Interconnect Cost Control during High-Level Synthesis
نویسندگان
چکیده
Architectural synthesis tools map algorithms to architectures under real time constraints and quickly provide estimations of area and performance. However, these tools do not take the VLSI circuit interconnection cost into account whereas this cost becomes predominant with the technology decrease and the application complexity increase. A new methodology that enables the interconnection cost to be controlled all along the architectural synthesis process is presented in this paper. First experimental results are presented.
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